1. Technical Field
The present invention relates generally to computer systems and in particular to data operations within a multiprocessor computer system. Still more particularly, the present invention relates to a method, system, and data processing system for handling data snoop operations within a multiprocessor computer system.
2. Description of the Related Art
The computer industry has made significant developments in integrated circuit (IC) technology in recent years. For example, ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) concept. The system-on-a-chip concept refers to a system in which, ideally, all the necessary integrated circuits are fabricated on a single die or substrate. An SoC IC includes various reusable functional blocks, such as microprocessors, interfaces (e.g., external bus interface), memory arrays, and DSPs (digital signal processors). Such pre-designed functional blocks are commonly called “cores”.
With a SoC, processed requests are sent from a core referred to as an initiator to a target (which may also be a core). An initiator (or master or busmaster as it is sometimes called) is any device capable of generating a request and placing that request on the system bus to be transmitted to a target. Thus, for example, either a processor or DMA controller may be an initiator.
Some initiators, called “caching-initiators”, internally cache copies of the contents stored in the targets. Notably, initiators are also typically able to snoop requests issued on the system bus by other initiators. To maintain data coherency between the cached values and the values stored in the targets, caching-initiators have a snoop port for snooping the contents of the cache when other initiators access the targets. Certain requests made by initiators may be “snoopable” by other initiators. Snoopable requests are delivered to one or more targets and are also broadcast to all the caching-initiators via the “snoop” bus. A “snooper” is the portion of a caching-initiator that attaches to the snoop bus. In current art, all “snoopers” of systems that support variable latency are required to provide a response to snoopable requests.
The system bus consists of an interface to the caching-initiators and a separate interface to the targets and logic between the interfaces. The logic between the interfaces is called a “bus controller”. This configuration is typical among system-on-a-chip (SoC) buses, where all the initiators, targets and the bus controller are on the same chip (die). In order to complete the connections between initiators and targets, the SoC includes an on-chip bus utilized to connect multiple initiators and targets. This bus is referred to as processor local bus (PLB) and has associated logic, PLB Macro. The “PLB Macro” is a block of logic that acts as the bus controller, interconnecting all the devices (i.e., initiators and targets) of the SoC.
The bus controller consists of a “request queue”, an arbiter, routing logic and miscellaneous buffering and registering logic. The “request queue” is a FIFO that holds a multitude of pending requests from an initiator. Requests, including snoopable requests, are pipelined by the initiators into the “request queue” of the bus controller. This means that a new request is sent by the initiator before any response is received for previous sent requests. Each request queue sends its output (the oldest request) to the arbiter. The arbiter selects which request is “granted” from among the pending requests from each of the request queues. When a request is “granted”, it is broadcasted to the snoopers and the targets. The routing logic directs the appropriate signals to/from the initiator associated with the granted request and the appropriate target.
Processors often utilize a mechanism known as hardware enforced cache coherency to ensure consistency of data when multiple processors cache the contents of main memory. A portion of this mechanism is known as “snooping”. When a processor makes an access to main memory, that access is first broadcast to all the other processors (the “snooping processors”) as a “snoop request” by a central resource (the “PLB Macro”). The snooping processors react to the snoop request by returning a snoop result that indicates the state of that processor's cache for the address provided with the snoop request. The “PLB Macro” receives all the snoop results and takes one of several possible actions based on the values of the snoop results.
Typically, all processors continuously snoop all main memory accesses to ensure data consistency. However, there are often cases when a processor doesn't need to or can not participate in snooping. The processor may be in one of several operating modes that prevent snooping. For example, the processor may be (1) executing non-shared code; (2) executing code in which data consistency is maintained by software (rather than hardware); (3) idle due to a temporary lack of work; or (4) undergoing a “soft reset” (resetting an individual processor while the remainder of the system continues to operate). There may be other reasons as well.
With current implementations, when a snoop request is broadcasted, all of the snoopers are expected to respond. Thus, the PLB macro waits until it receives a response from each snooper before proceeding with the task. This is done because the snoopers are allowed variable time for snooping. Notably, the current systems, in which all snoopers respond in a fixed time, do not require this feature. If any of the snoopers fails to provide a response, the bus controller continues polling that snooper for a response indefinitely causing the system to stall. Further, if bus traffic continues when a processor stops snooping, that processor's cache typically must be flushed and invalidated to ensure data consistency.
The present invention recognizes that in the above cases, it would be desirable to allow a processor to not snoop, while the other processors continue to snoop without stalling the entire system. A method and system where bus traffic continues while processors dynamically disable and re-enable snooping would be a welcomed improvement. It would be further desirable to provide a mechanism to ensure the system does not get stuck (stall) waiting for a snoop result that is never going to come because a snoop request is sent to a snooping processor while the processor is not snooping.